def write_port(self, *, domain="sync", granularity=None, src_loc_at=0):
        """Request a write port.

        The created write port is synchronous, updating the contents of the selected row at each
        :ref:`active edge <lang-sync>` of :py:`domain` where the enable input is asserted.

        Specifying a *granularity* when :py:`shape` is :func:`unsigned(width) <.unsigned>` or
        :class:`data.ArrayLayout(_, width) <.data.ArrayLayout>` makes it possible to partially
        update a memory row. In this case, :py:`granularity` must be an integer that evenly divides
        :py:`width`, and the memory row is split into :py:`width // granularity` equally sized
        parts, each of which is updated if the corresponding bit of the enable input is asserted.

        The signature of the new port is
        :py:`WritePort.Signature(shape=self.shape, addr_width=ceil_log2(self.depth), granularity=granularity)`.

        Returns
        -------
        :class:`WritePort`
        """
        if self._frozen:
            raise AlreadyElaborated("Cannot add a memory port to a memory that has already been elaborated")
        signature = WritePort.Signature(
            shape=self.shape, addr_width=ceil_log2(self.depth), granularity=granularity)
        return WritePort(signature, memory=self, domain=domain,
                         src_loc_at=1 + src_loc_at)
Request a write port.

        The created write port is synchronous, updating the contents of the selected row at each
        :ref:`active edge <lang-sync>` of :py:`domain` where the enable input is asserted.

        Specifying a *granularity* when :py:`shape` is :func:`unsigned(width) <.unsigned>` or
        :class:`data.ArrayLayout(_, width) <.data.ArrayLayout>` makes it possible to partially
        update a memory row. In this case, :py:`granularity` must be an integer that evenly divides
        :py:`width`, and the memory row is split into :py:`width // granularity` equally sized
        parts, each of which is updated if the corresponding bit of the enable input is asserted.

        The signature of the new port is
        :py:`WritePort.Signature(shape=self.shape, addr_width=ceil_log2(self.depth), granularity=granularity)`.

        Returns
        -------
        :class:`WritePort`
        
amaranth/lib/memory.py